This invention relates generally to the field of semiconductor and/or integrated circuit devices, and more particularly to a random access memory and process for writing to and reading from the same.
The primary object of the invention is to provide a random access memory that increases data throughput.
Another object of the invention is to provide such a random access memory that reduces the chip area dedicated to transmitting and/or storing address information.
Another object of the invention is to provide a random access memory and method of operating the same in which read and write operations may be executed in the same clock cycle.
Yet another object of the invention is to provide such a random access memory and method of operating the same in which fully random addresses may be employed.
Still yet another object of the invention is to provide such a random access memory and method of operating the same in which successive and/or asserted addresses may be completely unrelated.
Another object of the invention is to provide such a random access memory and method of operating the same in which no restrictions are placed on successive and/or asserted addresses.
Another object of the invention is to provide such a random access memory and method of operating the same in which the same address may be used to read from and write to the memory in the same clock cycle.
A further object of the invention is to provide such a random access memory and method of operating the same in which a periodic signal (e.g., a clock) is the only control-type signal essential to operability.
Other objects and advantages of the present invention will become apparent from the following description, taken in connection with the accompanying drawings, wherein, by way of illustration and example, embodiments of the present invention are disclosed.
The present invention concerns a random access memory comprising: a data input bus, a data output bus, a random access memory array configured to transfer data to random write addresses and from random read addresses in said random access memory array, an address bus providing said random read addresses and said random write addresses, and a periodic signal configured to control data transfer operations (i) to said random access memory array in response to a first transition or logic level of said periodic signal and (ii) from said random access memory array in response to a second transition or logic level of said periodic signal, wherein said second transition or logic level of said periodic signal is complementary to said first transition or logic level of said periodic signal.
In a further embodiment, the present invention concerns a process for reading data from and writing data to a random access memory array, comprising the steps of transferring a first plurality of data bits on a first unidirectional bus either to or from a first random address in said random access memory array in response to a first transition or logic level of a periodic signal, and transferring a second plurality of data bits on a second unidirectional bus either from or to a second, independent random address in said random access memory array in response to a second, complementary transition or logic level of said periodic signal (i.e., in the opposite manner from the first step).